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Espressif Systems /ESP32-C6-LP /LP_UART /CONF0_SYNC

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Interpret as CONF0_SYNC

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (PARITY)PARITY 0 (PARITY_EN)PARITY_EN 0BIT_NUM 0STOP_BIT_NUM 0 (TXD_BRK)TXD_BRK 0 (LOOPBACK)LOOPBACK 0 (TX_FLOW_EN)TX_FLOW_EN 0 (RXD_INV)RXD_INV 0 (TXD_INV)TXD_INV 0 (DIS_RX_DAT_OVF)DIS_RX_DAT_OVF 0 (ERR_WR_MASK)ERR_WR_MASK 0 (MEM_CLK_EN)MEM_CLK_EN 0 (SW_RTS)SW_RTS 0 (RXFIFO_RST)RXFIFO_RST 0 (TXFIFO_RST)TXFIFO_RST

Description

Configuration register 0

Fields

PARITY

This register is used to configure the parity check mode.
PARITY_EN

Set this bit to enable uart parity check.
BIT_NUM

This register is used to set the length of data.
STOP_BIT_NUM

This register is used to set the length of stop bit.
TXD_BRK

Set this bit to enbale transmitter to send NULL when the process of sending data is done.
LOOPBACK

Set this bit to enable uart loopback test mode.
TX_FLOW_EN

Set this bit to enable flow control function for transmitter.
RXD_INV

Set this bit to inverse the level value of uart rxd signal.
TXD_INV

Set this bit to inverse the level value of uart txd signal.
DIS_RX_DAT_OVF

Disable UART Rx data overflow detect.
ERR_WR_MASK

1’h1: Receiver stops storing data into FIFO when data is wrong. 1’h0: Receiver stores the data even if the received data is wrong.
MEM_CLK_EN

UART memory clock gate enable signal.
SW_RTS

This register is used to configure the software rts signal which is used in software flow control.
RXFIFO_RST

Set this bit to reset the uart receive-FIFO.
TXFIFO_RST

Set this bit to reset the uart transmit-FIFO.

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Register License

Copyright 2024 Espressif Systems (Shanghai) PTE LTD

Licensed under the Apache License, Version 2.0 (the “License”); you may not use this file except in compliance with the License. You may obtain a copy of the License at

http://www.apache.org/licenses/LICENSE-2.0

Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language governing permissions and limitations under the License.

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Register Reference

https://github.com/espressif/svd